As communication technologies evolve, data transfer speeds increase along with the amounts of data. These parameters continually push the demands of the data processing devices to provide for circuits that may handle more data with faster throughput.
At the same time, the semiconductor industry has been developing integrated circuits of greater density and smaller size. With these increased levels of integration and functionality within the smaller area devices, a greater premium exists on the availability of signal interfacing.
To assist these I/O needs, transceiver-multiplexing circuits may be used to replace parallel data lines with higher speed serial interfacing. Using a transceiver-multiplexing circuit, a receiver may receive a high-speed serial data sequence and then convert it into parallel data of a slower clock rate. Likewise, data that is to be sent out may be converted from a parallel format to a serial data stream.
To further enhance the data handling capability, the serial-to-parallel and parallel-to-serial transceivers may be disposed in parallel relationships on a given data-handling device. This structure may enhance the efficiency of the more highly integrated data processing applications of, e.g., encoded data processors or programmable circuits of a field programmable gate array (FPGA).
When receiving data of an external serial data stream, the transceivers may accommodate input data transfer speeds as high as 3-10 gigabits per second, or even higher. This speed of operation, in some instances, may be much greater than the internal operating speed of an embedded data processor/system. But use of the serial-to-parallel transceivers and conversion of the serial data into parallel data may effectively reduce the high-speed data rate of the serial stream to a slower rate.
For example, a serial data stream may be encoded with, e.g., “non-return to zero” encoding of a known protocol to assist clock recovery processes. It may arrive with a 3 gigabit per second (Gbs) data rate. Assuming an 8 bit/10 bit (non-return to zero) structure, a decode and clock recovery process may replace every 10 bits of the input stream with 8 bit recovered data and may establish a corresponding clock rate of about 2.4 Gbs. Subsequent serial-to-parallel conversion to 16 bits of parallel data may further reduce the effective data/clock rate from 2.4 Gbs to about 150 megabits per second. This lower data rate may be more easily accommodated by most off-the-shelf and/or “library” data processing circuits, systems and embedded components.
From the above example, the effective I/O pad count for an integrated circuit may be reduced by a factor of 16-to-1, or more commonly 8-to-1 when the serial data is a differential signal. That is, the pin count for the integrated circuit may be reduced proportionately in accordance with the conversion factor of the transceiver.
When working with fast input data streams, some communication systems may recover an input clock from transitions of the received input data (rather than accompany the data signal with an associated clock signal). Using known data encoding protocols, the data to be delivered may be encoded to assure a sufficient number of signal transitions that may support clock recovery. For example, eight bits of data may be encoded into a 10 bit sequence. The encoding may add additional transitions to facilitate AC-coupling and clock recovery. Thus, for example, a hexadecimal data “FF” (1111 1111), which might otherwise present eight consecutive high level conditions for serial propagation, may be alternatively encoded to a 10-bit sequence with additional zero states (101011 0001). The encoded 10-bit serial data stream encoded by such known encoding protocols may also help guarantee a DC-balance, which may be helpful when using AC coupling.
It may be further noted that the different data channels may present data to a receiver with different timing relationships. In other words, the data of one channel may be offset or “skewed” relative to the data of the other channels. Additionally, the frequency from which the data originated may not be coherently related to the internal operating frequency of the receiver. In other words, the data may originate from a transmitter having a clock frequency that may be different from that of the receiver and that may also drift over time.
Because the data of the separate parallel communication channels may not be aligned relative to each other at the receiver, and because the frequency associated with the received data may not be coherent to the internal operating frequency of the receiver; buffers may be required to buffer and align the data of the different channels. Additionally, the buffers may correlate the data that is recovered to an internal operating frequency of the receiver.